Electrical insulating layers are typically required in both discrete semiconductor devices and in integrated circuits. This invention is concerned with a process for producing a local insulating layer by the oxidation of a semiconductor material.
The local oxidation of silicon (LOCOS) has been widely used for large scale integrated (LSI) circuits because it presents several advantages such as improvement in packing density and compatibility with standard LSI processing. However, the conventional LOCOS process used to produce a silicon dioxide insulating layer results in the formation of a so-called "bird's beak" shaped structure on the borders of the silicon dioxide. This phenomena reduces the active width of the channels which are located between areas where the oxidation of silicon has occurred. This reduction in channel width is a major obstacle to the manufacturing of very large scale integrated (VLSI) circuits when devices are scaled down to the micrometer and submicrometer range. Thus, the fabrication of the bird's beak free device has been an essential objective for many future process and scaled device technologies.
Several prior art methods are known which achieve the growing of thick oxide with small or even zero bird's beak structures, as shown in Isaac, "Fabrication Process for full Box Isolation Without a Bird's Beak" IBM Technical Disclosure Bulletin, Vol. 22, No. 11 (Apr. 1980) pp. 5148-51, and Matsumoto, et al., "Method of Manufacturing Semiconductor Devices," U.S. Pat. No. 4,292,156 (Sept. 29, 1981).
In these methods a standard IC process is used to form islands of silicon in a silicon substrate by means of a first masking layer of silicon nitride. Then a second layer of silicon nitride is applied to seal the edges of the islands so that when the subsequent field oxidation step is performed, no oxide is produced immediately adjacent to the island, thus preventing the creation of a "bird's beak" due to lifting of the island edges. Unfortunately, silicon nitride and silicon are incompatible so it is necessary to add stress relief silicon dioxide (SRO) layers under each silicon nitride to prevent unwanted defect generation as illustrated by Isaac. However, each such added layer requires an added process step which increase both process complexity and cost.
FIGS. 1A and 1B illustrate the prior art fabrication process with the undesirable "bird's beak". The process shown is for a non-planar active silicon surface, but a similar problem exists in a planar process as well. A stress relief layer 10 of silicon dioxide (SRO) is first thermally grown on the silicon substrate 20. Then a masking layer 30 of silicon nitride is deposited on top of the SRO layer 10. The nitride layer 30 is then patterned to define the active areas 40 and the SRO layer 10 can be etched away in the field area 50 which was exposed during the nitride patterning. For a non-planar structure the surface of the active area 40 and the surface of the exposed field area 50 are in the same plane as shown in FIG. 1A. On the other hand if a final coplanar structure is desired, the field area 50 is further recessed by either a KOH chemical etch or a plasma etch process. In either case, the field area 50 is then oxidized 60 with the resulting structure as shown in FIG. 1B. The field oxidation 60 causes the nitride layer 30 to lift at the edges forming a "bird's beak" 70. The width of the active area 40 is thus reduced by a width DW on each of two sides. This narrowing of 2*DW can result in the active area 40 becoming completely inactive or unsuitable for fabrication of devices such as transistors, interconnects, and contacts as devices are decreased in size toward 1 micrometer dimensions.